Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
A design is conventionally instantiated in programmably configurable circuitry of an FPGA (“FPGA fabric”) using a hardware description language (“HDL”). However, implementing a design for concurrent processing using an HDL is a tedious task owing to maintaining a correct order of execution of data processing as data propagates through programmed programmable logic. Accordingly, a more convenient way to implement a user application in an FPGA for concurrent processing is needed.
Others have suggested using multiple microprocessors for concurrent processing. However, microprocessors conventionally are limited to a fixed set of instructions, and thus instructions outside of the fixed set may be slow to execute. Additionally, such microprocessors conventionally have to decode instructions as part of data processing, which slows processing.
Still others have suggested using multi-Application Specific Instruction Processor (ASIP) architectures, such as may be used in network processors. In for an ASIP architecture, a user's code is parsed to identify instructions not part of a set of conventional instructions. The instructions identified are then used to augment the decode logic of a conventional microprocessor to provide the set of conventional instructions with additional customized instructions. Conventionally, network processors use multi-threaded processing units with a customized instruction set and customized memory architectures. However, ASIP architectures are still limited with respect to concurrent processing by limitations of decoding instructions, as well as limited by the number of microprocessors.
To address a more robust programming environment, others have suggested programming in Handel-C to port C programs to FPGA fabric. However, Handel-C is conventionally a language that requires cycle accurate information, where each statement is associated with a single clock cycle. However, programmers may want to write a program listing to merely execute in a sequence without being limited to knowledge of clock cycle accurate information.
Accordingly, it would be desirable and useful to provide means for providing concurrent processing in an FPGA that avoids one or more of the above-mentioned limitations.